8,000 core chip?

[XoRn]

So what your saying... is... Intel has found a way to sell its users 80 crappy cores at the same time!?!?! Nice job Intel j/k. I'll have to wait and see how one of these runs. It makes me wonder though if Intel is doing this, is AMD also in the process of making one...

[gvblake22]

You've gotta expect that AMD and Intel are both hard at work developing newer, more advanced multi-core architectures as we speak. The benefit of that many cores is debatable, but I think the fact that it will be on a new architecture with new manufacturing processes and technology will give it a performance boost regardless of how many cores it has.

[Gig-O-Ram]

Originally Posted by Lead Head

It doesn't work that. You can't add clocks together like that. These CPUs are meant for extreme parallelism, processing very threaded applications. The individual cores are VERY SMALL and simple. Much much smaller then a normal CPU. The die is the size of a normal dual core, or maybe quad core chip, still on 65nm technology. The TDP of the chip is around 80 watts or so, smaller then Intel's current quad cores. The reason why we couldn't use these CPUs is because they are RISC, or Reduced Instruction Set, they usually can be very simple, and high performance per core. The Mac PowerPC line of computers were RISC. x86 is CISC, which is not compatible with RISC.

Relax, bro...I was joking about the clock speeds. I used to think similarly about hyper threaded and multi-core CPUs, until it was explained to me that the clock is spread over the entire architecture of the chip...or something to that effect. I don't think we'll see CPU cores that reach the terrahertz realm for a long, long time. And 25+ Thz? Not in our lifetime...

Ok...RISC = Reduced Instruction Set, so CISC must = Complex Instruction Set? I'm guessing on that one. Was I close?

[Lead Head]

Originally Posted by Gig-O-Ram

Relax, bro...I was joking about the clock speeds. I used to think similarly about hyper threaded and multi-core CPUs, until it was explained to me that the clock is spread over the entire architecture of the chip...or something to that effect. I don't think we'll see CPU cores that reach the terrahertz realm for a long, long time. And 25+ Thz? Not in our lifetime...

Ok...RISC = Reduced Instruction Set, so CISC must = Complex Instruction Set? I'm guessing on that one. Was I close?

Actually, I'm not entirely sure what CISC was myself, but A quick visit to the Acronym Finder confirms it is Complex Instruction Set

[Gig-O-Ram]

Originally Posted by Lead Head

Actually, I'm not entirely sure what CISC was myself, but A quick visit to the Acronym Finder confirms it is Complex Instruction Set

Seriously...I just took a guess on that! But I just thought that if S=Simple, then in the context of CPUs, C had to = Complex. It made sense...